semify combines deep expertise in FPGA and ASIC digital design and verification with RISC-V and its own edge AI platform, EdgeWave, to solve complex hardware challenges. Our senior engineers work directly in client teams across Europe and beyond, from RTL design and UVM-based verification to custom RISC-V extensions and edge AI acceleration. We also use AI in our own engineering, applying agentic AI to design conversion and verification so projects move faster and ship with greater confidence.
EdgeWave is semify's edge AI platform for real-time, low-power inference at the sensor. Full flow from TensorFlow model to FPGA or ASIC. Currently in development for an advanced acoustic application, built to scale across sensor domains.
Agentic AI for hardware engineering: AI-assisted VHDL-to-SystemVerilog conversion, testbench generation and verification. Built on deep UVM expertise and developed further in the FFG-funded VeriPy project.
We're looking for sensor, MEMS and industrial companies that want to bring AI directly into their sensor products. Our EdgeWave edge AI platform covers the full flow from TensorFlow model to ASIC or FPGA.
ASIC and FPGA design and verification, from spec to silicon. Senior engineers who own blocks, subsystems or full projects, lead teams and work directly with your stakeholders, or reinforce your team.
Domain-specific acceleration through custom RISC-V instructions, from ISA definition and RTL implementation to full verification. Our TRISTAN work was shown at RISC-V Summit Europe and DV Club Zurich.