AI-Assisted Hardware Design & Verification: Agentic AI for Faster Chip Development

Hardware design and verification is a major bottleneck in chip development. Verification alone often takes more than half of a project's effort. At semify, we combine many years of hands-on experience in ASIC and FPGA verification with agentic AI to speed up this work, while keeping engineers in control.

What we do

• AI-assisted design conversion: automated conversion of legacy VHDL code to SystemVerilog, with equivalence checking and verification

• Testbench generation: AI-supported creation of UVM environments, sequences and checkers from specifications

• Verification assistance: AI-supported test planning, coverage analysis and debug support

• Agentic workflows: AI agents built into existing EDA flows and connected to industry tools

Research-backed
semify is a partner in VeriPy, a research project funded by the Austrian Research Promotion Agency (FFG). VeriPy develops AI-assisted methods for VHDL-to-SystemVerilog conversion and verification. The project successfully completed its intermediate evaluation in 2026.

Why semify

• Engineers first: our AI work is built on real verification experience from real product projects, not on AI hype

• Results that can be trusted: every AI-generated output is checked with established verification methods

• Fits into your existing flow: our methods complement tools and methods you already use, such as UVM and formal verification

What we're looking for
We'd like to talk to companies that want to modernize legacy code, speed up verification or explore AI in their hardware development flow. We're also open to research partners who want to take AI-assisted chip design further.