Custom RISC-V Instruction Set Extensions: From ISA Definition to Verified Hardware

RISC-V allows processors to be extended with custom instructions tailored to a specific application, such as AI, signal processing or security. This can bring large gains in performance and energy efficiency compared to general-purpose cores. semify has hands-on experience in designing, implementing and verifying these extensions.

What we do

• ISA extension definition: analyzing the workload and identifying which instructions will speed it up

• RTL implementation: integrating custom instructions into existing RISC-V cores

• Verification: UVM-based and formal verification of the extended core, including compliance with the RISC-V specification

• Software enablement: toolchain support so the new instructions can be used from software

• Edge AI acceleration: custom instructions for efficient on-device neural network inference

Proven in TRISTAN
Within the TRISTAN project, semify developed custom RISC-V instruction set extensions together with an edge AI accelerator demonstrator. We showed this work at RISC-V Summit Europe 2026 in Bologna and presented it at DV Club Zurich 2026 at ETH Zurich.

Why semify

• Design and verification from one source: a custom instruction is only valuable if it is verified correctly

• Deep experience with the RISC-V ecosystem, including open-source cores

• Experience across the full path from architecture to verified RTL, on ASIC or FPGA

What we're looking for
We'd like to talk to companies that want to speed up specific workloads with RISC-V, add custom instructions to their own cores, or need support verifying RISC-V based systems. We're also interested in partners for joint research projects.