Agentic LLMs for on-chip systems design and synthesis

Institution: SDU, Centre for Industrial Mechanics, Sønderborg — available as a Danish beneficiary

Expertise: Chips and Systems Design, agentic LLMs for on-chip design synthesis; Verilog and VHDL generation, fine-tuning and benchmarking; HW/SW interface synthesis; HLS; hardware-aware code generation; embedded AI and edge ML

Concrete assets: Verilog and VHDL-Instruct datasets; hardware-aware LLM datasets and benchmarks for HDL and embedded code generation; testbench generation; quantised neural networks deployed on FPGA

What you offer: an AI-methodology work package, plus writing the RAISE justification page (section 11 of Part B2), open for proposition

Supervision capacity: 3 PhD student, 1 research engineer, 2 research assistants, 4 master's students