Register Manager

Register Manager, the flagship product of Jade Design Automation, efficiently manages all tasks around the HW/SW interface of an SoC. The users can capture register and bitfield information on the IP level as well as the memory maps on the IP, subsystem and SoC level. It generates RTL, Verification, SW, Documentation and Interoperability formats like IP-XACT 1685-2009 and 1685-2014 from these descriptions. On top of the IP-XACT and SystemRDL importers, legacy data in custom formats can be imported via the tool’s API.

Register Manager has a rich and intuitive GUI to instantly visualize and edit the HW/SW interface. The tool also has a fully functional shell mode for power users as well as fully scriptable command files for automated flows. Register Manager had out-of-box support for Arm’s TrustZone® technology. It is lightweight and performant and can capture, validate, generate Verilog, UVM, C-headers and documentation for a IoT SoC in a few seconds.

The tool addresses the requirements of System Architects who can capture the high level design in a top-down approach. It is also a great productivity booster for IP teams who can auto-generate production ready Verilog and UVM register descriptions throughout the development process. System Integrators can use the tool to pull together IPs from various sources to a single platform to increase the quality of the system.