CHERI-based RISC-V single-board computer (SBC) platform

Company stage: Pre-prototype. Seeking investment to build the first hardware prototype — no working prototype exists yet.

Research category: Experimental Development

Sector fit: Theme 3 (Convergence of ACT and Semiconductor technologies) — Investor Partnerships ACT & Semiconductors competition

Problem and solution: Most security vulnerabilities in embedded and connected systems stem from memory-safety failures. CHERI (Capability Hardware Enhanced RISC Instructions) enforces memory and capability protection directly at the processor level, closing off this class of vulnerability. This project builds a single-board computer (SBC) on a CHERI-enabled RISC-V processor, giving hardware-enforced protection conventional SBCs don't offer. Its requirements — modest processor power, standard SBC form factor and interfaces — are generic across a broad range of embedded and edge-compute use cases.

Technology / innovation: A 64-bit, SBC-class board differentiated from conventional SBCs by its CHERI-enabled RISC-V processor. It supports a standard set of interfaces (e.g. USB, HDMI) suitable for general-purpose secure use rather than a single-purpose module.

Market awareness / wider applications: Applicable wherever standard SBCs are used but stronger hardware security is needed — for example ACT/semiconductor systems, critical national infrastructure (CNI), and industrial/process control.

Investor fit: MCA is seeking an investor partner who sees the opportunity in the platform as a standalone product across multiple markets, not just a single application — suited to a multi-phase hardware play rather than a one-off project investment.

IP / competitive advantage: Specialist expertise in capability-based hardware security. The platform is 64-bit and SBC-class, aimed at application-processor-level workloads rather than microcontroller-class tasks.

Traction / track record: No prototype currently exists. This is a pre-prototype opportunity: the requested investment funds design and build of the first hardware prototype.

Team: Dr Divya Atkins (Managing Director) — DPhil Computer Science (York), MSc Computing (Oxford), background in high-integrity safety-critical/embedded real-time systems and security. Dr Martin Atkins (Technical Director) — DPhil Computer Science (York), specialist in safety-critical development, formal verification test infrastructure, rapid prototyping and OpenSource.