ProductUpdated on 13 November 2025
Riviera-PRO
Field Application Engineer at Aldec
Poland
About
High-Performance Simulator for Advanced Verification of Mixed Language Designs
IEEE VHDL, SystemVerilog, Verilog-AMS, SystemC/C/C++
Verification Libraries: UVM, OS-VVM
Assertion-Based Verification: SVA, PSL
Looking for
- License partner
Applies to
- IT solutions and software
Organisation
Similar opportunities
Service
UVM-Based Testbench & Verification Services
- Space
- Software
- Consulting
- Technology Transfer
- Testing & Analysis Other
Silvia Candia
CEO at Nytt UK
Exeter, United Kingdom
Project cooperation
UVM-Based Testbench & Verification Services
- Space
- Space technology
- Earth observation
- Space exploration
- Satellite navigation
- Measurement, testing, proofing, diagnostic systems
Silvia Candia
CEO at Nytt UK
Exeter, United Kingdom
Project cooperation
Professional FPGA Hardware Design Solutions – VHDL & Verilog
- Space
- Space technology
- Earth observation
- Engineering service
- Measurement, testing, proofing, diagnostic systems
Silvia Candia
CEO at Nytt UK
Exeter, United Kingdom